This invention relates to an improvement of a semiconductor integrated circuit for a stabilized power supply circuit which is required to stably supply a voltage even when a load is largely changed in level.
FIG. 5 is a block diagram of a stabilized power supply circuit which serves as the premise of the invention.
An input voltage V.sub.I is supplied to the emitter of a FNF transistor Q.sub.10. The output voltage V.sub.O from the collector of the transistor is applied via a resistance R.sub.O of a lead conductor to a load R.sub.L through which a load current I.sub.O flows.
A stabilized power supply circuit 3 is connected to the base of the transistor Q.sub.10 and controls the transistor so that the output voltage V.sub.O is kept constant.
The stabilized power supply circuit 3 is incorporated in a semiconductor integrated circuit (IC).
The stabilized power supply circuit 3 comprises a reference voltage circuit 1, an error amplifier 2, an output transistor Q.sub.3, potential dividing resistors R.sub.A and R.sub.B, etc.
The output voltage V.sub.O of the transistor Q.sub.10 is divided by the resistors R.sub.A and R.sub.B. The intermediate voltage V.sub.A is input to a negative terminal of the error amplifier 2 which is connected to base of the output transistor Q.sub.3.
The reference voltage circuit 1 receives the input voltage V.sub.I and outputs a reference voltage V.sub.ref which is then input to a positive terminal of the error amplifier 2. The output of the error amplifier 2 is supplied to the base of the output transistor Q.sub.3.
In this way, the voltage V.sub.A which is a portion of the output voltage V.sub.O is fed back to the base of the output transistor Q.sub.3, and the output transistor Q.sub.3 is controlled on the basis of the difference between the reference voltage V.sub.ref and the voltage V.sub.A so as to stabilize the output voltage V.sub.O.
FIG. 6 is a circuit diagram of an example of the reference voltage circuit 1.
The input voltage V.sub.I is coupled via a resistor R.sub.3 to the collector of a transistor Q.sub.1 which is connected so as to function as a diode. The emitter of the transistor Q.sub.1 is grounded. The input voltage V.sub.I is coupled via a resistor R.sub.2 also to the collector of a transistor Q.sub.2. The emitter of the transistor Q.sub.2 is grounded via a resistor R.sub.1. The bases of the transistors Q.sub.1 and Q.sub.2 are connected to each other so that the transistors Q.sub.1 and Q.sub.2 constitute a current mirror circuit. When the emitter area of the transistor Q.sub.2 is greater than that of the transistor Q.sub.1, the base-emitter forward voltage of the transistor Q.sub.2 can be made smaller than that of the transistor Q.sub.1 in the case where the same emitter current flows through both the transistors.
A current mirror circuit is used in a reference voltage circuit of another type. Since transistors used in a current mirror circuit must be highly consistent with each other, an IC chip incorporating such a circuit is designed so that these transistors are disposed as close as possible to each other. In order that these transistors operate at the same temperature, furthermore, such an IC chip is designed so that these transistors are separated as equally as possible from an output transistor or the like which may serve also as a heat generating source.
FIG. 7 shows an example of such an IC of the stabilized power supply circuit 3. In the chip, the distances L.sub.1 and L.sub.2 between the output transistor Q.sub.3 and the transistors Q.sub.1 and Q.sub.2 which constitute a current mirror circuit are substantially equal to each other.
Between the input voltage V.sub.1 and the ground, connected is a differential amplifier which consists of transistors Q.sub.6 and Q.sub.7 and is connected to a current mirror circuit consisting of transistors Q.sub.4 and Q.sub.5. The output of the differential amplifier is supplied to the base of a transistor Q.sub.8 which in turn outputs the reference voltage V.sub.ref.
The base of the transistor Q.sub.6 is connected to the collector of the transistor Q.sub.1, and the base of the transistor Q.sub.7 is connected to the collector of the transistor Q.sub.2. The emitters of the transistors Q.sub.6 and Q.sub.7 are grounded.
The reference voltage V.sub.ref which is output from the transistor Q.sub.8 is input to the positive terminal of the error amplifier 2.
Generally, the gain of the error amplifier 2 shown in FIG. 5 is not infinite. Therefore, the output voltage of the stabilized power supply circuit is varied when the load is changed in level, or lowered as the load becomes larger.
For example, it is supposed that the load current I.sub.O is changed from 0 A to 1 A in the circuit of FIG. 5, and the voltage V.sub.A is lowered from V.sub.A .apprch.V.sub.ref at I.sub.O =0 A to V.sub.A =V.sub.ref -10 mV at I.sub.O =1 A (in this case, V.sub.ref =1.25 V) because the gain of the error amplifier 2 is not infinite. When I.sub.O =0 A, the output voltage V.sub.O is obtained by the following expression: ##EQU1## In contrast, when I.sub.O =1 A, the output voltage V.sub.O is obtained by the following expression: ##EQU2## As seen from the above expressions, when the load current I.sub.O is changed from 0 A to 1 A, there arises an inconvenience that the output voltage is lowered by about 0.8%. This is indicated by a line L11 in FIG. 4 which shows the load variation characteristic of the output voltage V.sub.O.
This reduction of the output voltage seems to be caused by the fact that the gain of the error amplifier 2 is not infinite.
It is not necessary to particularly consider the transistors Q.sub.4, Q.sub.5, Q.sub.6 and Q.sub.7 in FIG. 6, because the effect of the heat generating source exerted on them is smaller than that exerted on the transistors Q.sub.1 and Q.sub.2.